Electrical simulation - Wave Technology Inc.

【Physical image of package】
	* Define RLC of package before simulation. This RLC includes gold bonding wire ~ wiring on PCB ~ through hole (T/H) ~ land and up to ball.

【Electrical image of package】
~Ladder Model~

R: Resistance [Rs: Resistance]
L: Inductance [Ls: Self Inductance, Lm: Mutual Inductance]
C: Capacitance [Co: Self Capacitance, Cm: Mutual Capacitance]

2. Simulation Sample

■LCR extraction simulation of 113pin BGA


		Top view	Bottom view


Top view	Bottom view	Top view	Bottom view

LCR： Wire ~ Wire Pattern~ Through Hole ~ Ball

Top view

Bottom view

	Chip_Pad	Device Pin	R	L	C
	Number	Number	(mohm)	(nH)	(pF)
	1	B2
	2	C4
	3	B1
	4	C3
	5	C2
	6	D3
DVSS	7	C1
IOVDD	8	D1
	9	D2
	10	E2
	11	E1
	12	E3
	13	E4
	14	F1
	15	F2
	16	F3
	17	G2
DVDD	18	G1
DVSS	19	H1
	20	F4
IOVDD3	21	J1
	22	H2
	23	G3
	24	G4
	25	K1
	26	J2
	27	H3
	28	J3
	29	K2
	30	H4
	・
	・
	・
	・
	・

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